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This ZIP File is associated with Rev 0 of the Application Note


    Using Cache on ADSP-SC5xx/ADSP-215xx SHARC+ Processors (EE-400)  


that can be found at http://www.analog.com/ee-notes.


Date Created:	May 26th, 2017


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It contains the example codes for configuring L1 Instruction and Data Cache on SHARC+ Core. 
The versions work on ADSP-SC589/ADSP-SC573 targets as configured in the project options

Example-1 : Locking of Data Cache By way.

Example-2 : Cache write-back and write-through policy

Example-3 : Configure Range registers and CCES cache support functions like flush_data_buffer.

Example-4 : Address range based cache invalidation ADSPSC573

Example-5 : DM-PM Coherency in Cache.

Example-6 : Maintaining data coherency between core and DMA by flushing cache before DMA.

Example-7 : Maintaining data coherency between core and DMA by disabling cache.

Refer to the readme.txt for more details on each project.


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All code examples have been written and tested with

	CrossCore Embedded Studio 2.5.0

	ADSP-SC589 revision 1.0	EZ-KIT Lite revision 1.2

	and 

	ADSP-SC573 revision 0.0 EZ-KIT Lite revision 1.0

	as applicable in the Project settings


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